1. Field of the Invention
This invention relates to improvements in electronic circuitry, and more particularly to circuitry and techniques for voltage level adjusting, controlling, and setting.
2. Relevant Background
In many applications, it is desirable or necessary to adjust or shift a voltage level from one electronic stage to an adjacent stage. For example, it is often desirable to shift TTL voltage levels, typically on the order of 0 to 5 volts, to higher voltage levels, for instance, on the order of 0 to V.sub.SHFT, where V.sub.SHFT may be 40 volts, or more. However, in the past, level shifters, and particularly, level shifters that use integrated slope control resistors can be susceptible to latching in one state. This, of course, is undesirable.
More specifically, a level shifter circuit 10, which can be used to drive a large output MOSFET (not shown), according to one prior art embodiment is shown in FIG. 1. The circuit 10 includes four MOS transistors 11-14. Transistors 11 and 12 are, in the embodiment shown, p-channel MOS devices connected between a voltage source, V.sub.SHFT, 16 and output nodes 18 and 20. Transistors 13 and 14, on the other hand, are n-channel MOS transistors, which are connected respectively between the output nodes 18 and 20 to a reference potential or ground 22.
An input signal or voltage level on line 24 is applied to the gate of transistor 14, and is inverted by an inverter 26 and applied to the gate of the N-channel transistor 13. The gate of the p-channel transistor 12 is connected to the output node 18, and the gate of the p-channel transister 11 is connected to the output node 20.
The switching speed of this level shifter will only be a function of the on-resistance of transistors 12 and 14 and the gate charge characteristic of the output MOSFET. As a result, the switching speed may be extremely fast, which may be undesirable, especially when the output is used to drive loads that are prone to cause electromagnetic interference (EMI) due rapidly changing currents in long wires.
To address this problem, a circuit such as the circuit 30 shown in FIG. 2, has been proposed. The level shifting circuit 30 includes four transistors, 32-35 connected in series between a voltage, V.sub.SHFT 38 and a reference potential such as ground 40. The gate of p-channel transistor 32 is connected to the drain of the p-channel transistor 33 and, likewise, the gate of the transistor 33 is connected to the drain of transistor 32.
The input line 42 is connected to the gate of the n-channel transistor 35, is inverted by an inverter 44, and is connected to the gate of the n-channel transistor 34. In the circuit embodiment 30 of FIG. 2, a resistor 46 is provided between the drain of the p-channel transistor 33 and the output node 48. In addition, a resistor 50 is connected between the output node 48 and an output terminal 52, which may be connected to drive a large MOSFET transistor (not shown), or other appropriate load.
In the circuit 30 of FIG. 2, the switching speed is not instantaneous, but is a function of the values of resistors 46 and 50, since the on-resistance of the transistors 33 and 35 is negligible compared to-the resistances of resistors 46 and 50.
Although the circuit 30 of FIG. 2 addresses the above problems caused the instantaneous switching time, the circuit 30 has two problems. The first problem is that while the rise time of the output of the circuit 30 is a function primarily of the value of resistance 50, the fall time of the output is a function primarily of the series combination of the resistors 46 and 50. This makes setting the fall time with precision difficult. The second, and more serious, problem is that the ability of the level shifter circuit 30 to switch states is predicated on the ability of transistor 35 to pull the drain of transistor 33 down to the ground potential. This simultaneously switches transistor 32 on. If the value of resistor 50 becomes too large, the operation of the level shifter circuit 30 may be compromised.